Electrical Requirements for Blade Server BSC
By Greg Lopp, April 2003
Contents:
1. Introduction
1.1 Blade Support Chip
2. BSC Communications to System Service Processors
2.1 Asynchronously Based Functions
2.2 Read-Based Functions
2.3 Write-Based Functions
2.4 Clear-Based functions
2.5 System-Level
2.6 Temperature Alarm Thresholds
3 Power Sequencing and Reset
3.1 BSC Operating Mode
3.2 BSC Operating Frequency
3.3 BSC Signal List by Function
3.4 BSC Signal List by Pin Number
4 I2C Map
5 BSC Serial Ports
6 BSC Reset Control
7 Blade Server Power Circuitry
8 References
1. Introduction
This document describes the electrical interface requirements of the Blade Support Chip (BSC) for specialized Blade Server FRUs intended for use in the Sun Fire B1600 Blade system chassis. The content is intended for electrical engineers responsible for designing new solution-based products. Readers should reference other documents in the Blade Computing Development Kit, as shown in the References section of this document.
The Blade Support Chip signals and drawings in this document are for reference design only. The BSC is an 8-bit microcontroller and is used for system management interface to the low level of each Blade Server FRU. The BSC supports two serial ports for communications to the system service processors (SSPs).
The BSC is required on each Blade Server FRU to handle out-of-band communication. This communication covers the power up and hot swap, indicators, and read/write/async status of the Blade Server FRU. Sun is making available a BSC module code with jump table entries for interface to other program code. The bsc.c source code is available under a source-level agreement; please contact your account manager for assistance. Please send comments to: blade-dk-help@sun.com.
1.1 Blade Support Chip
This device is a Hitachi H8S/2148 microcontroller, part number HD64F2148AFA20.
The BSC provides the following features:
- Dual access (for Blade Server and SSPs) to board OS/FRU ID EEPROM
- Communication channel between Blade Server and SSPs
- Controls reset to the processor
- Controls the Indicators Power, Service_Required, and ready-to-remove LEDs
- Field-upgradable firmware, via host interface
- Implements a watchdog function for the board OS
- Monitors the speed of the fan, chip, and system temperature and voltage rails
- Communicates with the board OS via the X-Bus
- Accesses the FRU ID and DIMM SPD EEPROMs
2 BSC Communications to System Service Processors
The serial communications provide a command and control function classified as out-of-band. These communications handle start-up, data exchange, and event logging, and can be classified in four primary communication functions:
- Async -- the SSP will be notified asynchronously when the data changes.
- Read -- the SSP can query current status or read data.
- Write -- the SSP can initiate a change or write data.
- Clear -- the SSP can clear the event or log.
2.1 Asynchronously Based Functions
The BSC forwards all async events to the SSP and informs the SSP of other data changes. The BSC maintains an event log, stored in EEPROM, of 256 characters. Management data includes Blade Server chips' core temperature and Blade Server FRU ambient temperature. The BSC maintains programmable thresholds to set and clear fault events related to temperatures, fan speed, and/or voltages from the DCDC converters. The BSC also monitors all watchdogs on Blade Server FRU.
- Power status
- Watchdogs
- Blade Server CPU signatures
- Management data
- Host console
- Blade Server FRU ID
- BSC resets
- BSC faults
2.2 Read-Based Functions
- Power status
- Watchdogs
- Blade Server CPU signatures
- Post failure status
- Panic information
- Error reports
- Self diagnosis
- Management data
- Host console
- Console history
- Host ID
- MAC addresses
- Real-time clock
- Boot mode
- Watchdog timeouts
- Blade Server FRU ID
- Firmware upgrade (version)
- EEPROM config
- BSC resets
- BSC faults
- Firmware version
- Event log
- Current temperature
- Current fan speeds
- Monitor limits temperature
- Monitor limits fan speeds
- Monitor limits voltages
- Indicator LED states
- Voltage DCDC converters
- BSC self-test results
- SSP heartbeat
2.3 Write-Based Functions
- Power on
- Power off
- Resets
- Console break
- Management data
- Host console
- Host ID
- Real-time clock
- Boot mode
- Watchdog timeouts
- Blade Server FRU ID
- Firmware upgrade (upgrade)
- EEPROM config
- Monitor limits temperature
- Monitor limits fan speeds
- Monitor limits voltages
- Indicator LED
- BSC self-test initiate
2.4 Clear-Based Functions
2.5 System-Level
A summary list of the BSC commands and messages follows.
BSC Table:
- Host and power control
- Bootmode
- Eventlog
- CPU signatures (a limited subset will be used for Blade Servers)
- ASR and watchdogs
- Other BSC functions (Nvramrc2, FRU ID, CONSOLE LOG)
- BSC software element data (version)
- BSC reset events (poweron, wdreset, reset)
- RTC real-time clock
- Universal time code (epoch) format
fanTable:
- ShowFans
- ReadFanThreshold
- SetFanThreshold
tempTable:
- ShowTemps
- SetTempWarningThreshold
- ReadTempWarningThreshold
- ReadTempShutdownThreshold
- SetTempShutdownThreshold
- ReadTempPoweroffThreshold
- SetTempPoweroffThreshold
voltageTable:
- Show Voltages
- Set Voltage margin Thresholds
- Read Voltage margin Thresholds
ledTable:
debugTable:
- BSC eeprom reset
- BSC firmware upgrade
2.6 Temperature Alarm Thresholds
The BSC monitors two actual temperatures measured on the Blade Server FRU. One is designed to monitor the hottest ASIC mount on the Blade Server FRU. The second is intended to monitor the Blade Server FRU enclosure at the temperature sense chip, which is located at the hottest point within the Blade Server FRU.
The BSC compares these measured values to the thresholds programmed into the FRU ID EEPROM, and generates alarms that are sent to environmental monitoring software, which provides the option of shutting down the Blade Server automatically if a critical temperature is exceeded. Fatal thresholds result in immediate power off of the Blade Server without orderly OS shutdown. The programmed thresholds are shown in the following diagram.
Temperature ThresholdValue in Degrees C
CPU High Non-Critical+95C
CPU High Critical+110C
CPU High Fatal+120C
CPU Low Non-Critical0C
CPU Low CriticalNot Required
CPU Low FatalNot Required
Enclosure High Non-Critical+65C
Enclosure High Critical+75C
Enclosure High Fatal+75C
Enclosure Low Non-Critical+3C
Enclosure Low CriticalNot Required
Enclosure Low FatalNot Required
Figure 1: Programmed Temperature Thresholds
3 Power Sequencing and Reset
The BSC is powered by 5VSB as soon as the Blade Server is fully inserted into the midplane. When instructed by the SSP, it then turns on the rest of the DC/DC converters to provide power to the remainder of the Blade Server.
The BSC reset signal is derived from a simple power-on reset (POR) generator, which monitors the 5VSB rail.
3.1 BSC Operating Mode
The H8S/2148 is capable of operating in several modes, selected by the MD[1:0] pins. In this application the BSC is operated in Mode 2.
Four separate host interfaces are implemented, each of which has its own interrupt and chip-select.
The chip selects are derived from a single South Bridge programmable chip-select signal (PCS0#) with the individual selects CS[4:1]# being decoded using a '139 logic IC.
Two of the four available BSC interrupt requests are connected to interrupt inputs on the South Bridge.
Host InterfaceChip SelectBSC IRQSouth Bridge PCI InterruptPC Interrupt
(programmed in South Bridge)Address Offset
0CS1#HIRQ1INTC#IRQ90,1
1CS2#HIRQ11--2,3
2CS3#HIRQ3--4,5
3CS4#HIRQ4INTD#IRQ56,7
Figure 2: BSC Operating Mode
3.2 BSC Operating Frequency
In this application the BSC operates at 19.6608 MHz. This frequency is chosen to minimize serial port baud-rate errors and to maximize operating frequency.
3.3 BSC Signal List by Function
Note: Some signals are referred to as 'LOM'. This is to enable a common description with the SSP and other platforms that use the BSC/LOM firmware. Shaded fields in the following diagram indicate differences from the Blade Server BSC.
FunctionSymbolLOM FunctionNote
HOST INTERFACE
HOST_CS/Host Parallel Interface Chip SelectX-BUS
HOST_WR/Host Parallel Interface Write StrobeX-BUS
HOST_RD/Host Parallel Interface Read StrobeX-BUS
HOST_D{7:0}Host Parallel Interface Data BusX-BUS
HOST_A0Host Parallel Interface Address Bus (only Bit 0 used)X-BUS
HOST_IRQ{1,4}Host Interrupt RequestSouth Bridge
HOST_POR/Initialization ResetNot Used
HOST_XIR/XIRNot Used
HOST_SDAI2C Expansion Bus DataNot Used
HOST_SCLI2C Expansion Bus ClockNot Used
MANAGEMENT INTERFACELOM_TXD0,1Management Interface Transmit DataTo SSPs
LOM_RXD0,1Management Interface Receive DataTo SSPs
LOM_CTSManagement Interface Clear To SendNot Used
LOM_RTSManagement Interface Ready To SendNot Used
LOM_DTRManagement Interface Data Terminal ReadyNot Used
LOM_DSRManagement Interface Data Set ReadyNot Used
LOM_DCDManagement Interface Data Carrier DetectNot Used
CNSL_TXDConsole Transmit DataSouth Bridge
CNSL_RXDConsole Receive DataSouth Bridge
CNSL_CTSConsole Clear To SendSouth Bridge
CNSL_RTSConsole Ready To SendSouth Bridge
CNSL_DTRConsole Data Terminal ReadySouth Bridge
CNSL_DSRConsole Data Set ReadySouth Bridge
CNSL_DCDConsole Data Carrier DetectSouth Bridge
SER_ENABLE_LEnable Serial Outputs to SSPsFrom BSC
HOST POWER STATE
MANAGEMENTPWRBTN/ACPI Power Button SignalSouth Bridge
PWRGDHost Power Present outputFrom DCDC
ENVIRONMENTAL
MANAGEMENTFAN_SPEEDBSC Fan Tacho Frequency SignalsFAN1_SPEED
ENV_INT/Environmental Warning Interruptfrom ADM1021
V{5:0}_MONBSC Voltage Monitors (analog signals) Voltage Range - 0V to VREF
VREFBSC ADC Reference Voltage (analog signal)2.5V
V0_MONMultiply by 0.4 (Resistive divider 3K3 + 2K2)5V
V1_MONMultiply by 0.6 (Resistive divider 2K2 + 3K3)3V3
V2_MONMultiply by 0.8 (Resistive divider 820 + 3K3)2V5
V3_MON1:1 Ratio (no divider)Vcore
V4_MON1:1 Ratio (no divider)VTT
V5_MON1:1 Ratio (no divider)Not Used
MARGIN_CORE_UP/Used during testing to raise the DCDC output voltage (active-low)Vcore supply
MARGIN_CORE_DOWN/Used during testing to lower the DCDC output voltage (active-low)Vcore supply
MARGIN_2V5_UP/Used during testing to raise the DCDC output voltage (active-low)2V5 supply
MARGIN_2V5_DOWN/Used during testing to lower the DCDC output voltage (active-low)2V5 supply
MARGIN_3V3_UP/Used during testing to raise the DCDC output voltage (active-low)3V3 supply
MARGIN_3V3_DOWN/Used during testing to lower the DCDC output voltage (active-low)3V3 supply
MARGIN_5V_UP/Used during testing to raise the DCDC output voltage (active-low)5V supply
MARGIN_5V_DOWN/Used during testing to lower the DCDC output voltage (active-low)5V supply
STATUS MANAGEMENTPOWER/Power Flag (active-low)To LED
SERVICE_REQUIRED/Service Required Flag (active-low)To LED
READY_TO_REMOVE/R2R Flag (active-low)To LED
SYSTEM INTEGRATIONMD{1:0}Mode Setting Bits (used during programming)
LOM_XIN{+,-}19.6608MHz Crystal
LOM_RST/Power-On Reset to the BSCFrom Reset Gen.
CPU_RST/Power On Reset to the CPUTo North Bridge
SB_RST/Power On Reset to the South BridgeNot Used (Output)
PCI_RST/PCI Reset from the CPUNot Used (Pull-Up)
LOM_SDAPrivate I2C Expansion Bus DataEEPROM and CPU Temp
LOM_SCLPrivate I2C Expansion Bus ClockEEPROM and CPU Temp
HOST_SCAPrivate I2C Expansion Bus DataDIMM SPDs
HOST_SCLPrivate I2C Expansion Bus ClockDIMM SPDs
SUPPLY RAILS+5VSBMain Supply Rail, normally the PSU Auxiliary Supply +5V +/-5%
GNDGround Return
Figure 3: BSC Signal List by Function
3.4 BSC Signal List by Pin Number
PinBSC FunctionLOM FunctionClassCommentUsage
1RES/LOM_RST/InputActive-LowFrom Reset generator
2XTALLOM_XIN-Input 19.6608MHz Xtal
3EXTALLOM_XIN+Input 19.6608MHz Xtal
4VCCB5VSBSupply 5VSB
5MD1MD1Input Pull-Down
6MD0MD0Input Pull-Up (down for boot)
7NMIPWRGD/InputFalling-Edge TriggeredFrom DCDC
8STBY/LOM_STBY/InputActive-LowPull-Up
9VCC5VSBSupply 5VSB
10PA7SERVICE_FLAG/OutputActive-LowSERVICE_REQ LED
11PA6POWER_FLAG/OutputActive-LowPOWER LED
12SCL0LOM_SCLOutputActive-Low, Open-DrainI2C bus
13RXD0CNSL_RXDInputActive-LowTo Sbridge COM1
14TXD0CNSL_TXDOutputActive-Low, Tri-StateTo Sbridge COM1
15VSSGNDSupply 0V
16SDA0LOM_SDAI/OActive-Low, Open-DrainI2C bus
17P96LOM_DSRInputActive-LowNot Used
18CS1/HOST_CS1/InputActive-LowDecoded Xbus addr
19IOW/HOST_WR/InputActive-LowXbus - South Bridge
20PA5HOST_XIR/OutputActive-Low, Open-DrainNot Used
21PA4HOST_POR/OutputActive-Low, Open-DrainNot Used
22IOR/HOST_RD/InputActive-LowXbus - South Bridge
23IRQ0/Not UsedInputActive-LowPull-Up
24IRQ1/Not UsedInputActive-LowPull-Up
25IRQ2/Not UsedInputActive-LowPull-Up
26TMIXSED_FAN_TACHInputActive-High, Internal Pull-UpFrom Blade fan tacho
27P61PWRGDInputActive-High, Internal Pull-UpFrom DCDC
28TMIYCPU_FAN_TACHInputActive-Low, Tri-StateFrom CPU fan tacho
29P63Not UsedInputActive-High, Internal Pull-UpNot Used
30PA3PWRBTN/OutputActive-Low, Open-DrainTo Super IO
31PA2READY_FLAG/OutputActive-LowRdy-To-Remove LED
32P64LOM_RTSOutputActive-LowNot Used
33P65CNSL_DCDOutputActive-Low, Tri-StateTo Sbridge COM1
34P66Not UsedI/OActive-Low, Tri-StatePull-Up
35P67Not UsedI/OActive-Low, Tri-StatePull-Up
36AREFVREFInput
37AVCC5VSBSupply 5VSB
38AN0V0_MONInput 5V
39AN1V1_MONInput 3V3
40AN2V2_MONInput 2V5
41AN3V3_MONInput Vcore
42AN4V4_MONInput VTT
43AN5V5_MONInput Not Used
44P76CNSL_DTRInputActive-LowTo Sbridge COM1
45P77CNSL_RTSInputActive-LowTo Sbridge COM1
46AVSSGNDSupply 0V
47PA1CNSL_DSROutputActive-Low, Tri-StateTo Sbridge COM1
48PA0CNSL_CTSOutputActive-Low, Tri-StateTo Sbridge COM1
49TxD2TXOutputActive-LowTo SSP1 via Midplane
50RxD2RXInputActive-LowTo SSP1 via Midplane
51SDA1HOST_SDAI/OActive-Low, Open-DrainTo DIMM SPD via Mux
52HIRQ11HOST_IRQ11OutputActive-High, Totem-poleNot Used
53HIRQ1HOST_IRQ1OutputActive-High, Totem-poleSouth Bridge
54HIRQ12ALERT/InputActive-LowFrom ADM1021
55PWX0Not UsedOutput Not Used
56PWX1Not UsedOutput Not Used
57PB7Not UsedInputActive-High, Internal Pull-Up if not usedNot Used
58PB6Not UsedInputActive-High, Internal Pull-Up if not usedNot Used
59VCC5VSBSupply 5VSB
60P27MARGIN_5V_DOWN/OutputActive-Low, External 10K Pull-UpTo voltage margin
61P26MARGIN_5V_UP/OutputActive-Low, External 10K Pull-UpTo voltage margin
62P25MARGIN_3V3_DOWN/OutputActive-Low, External 10K Pull-UpTo voltage margin
63P24MARGIN_3V3_UP/OutputActive-Low, External 10K Pull-UpTo voltage margin
64P23MARGIN_2V5_DOWN/OutputActive-Low, External 10K Pull-UpTo voltage margin
65P22MARGIN_2V5_UP/OutputActive-Low, External 10K Pull-UpTo voltage margin
66P21MARGIN_CORE_DOWN/OutputActive-Low, External 10K Pull-UpTo voltage margin
67P20MARGIN_CORE_UP/OutputActive-Low, External 10K Pull-UpTo voltage margin
68PB5Not UsedInputActive-High, Internal Pull-Up if not usedNot Used
69PB4Not UsedInputActive-High, Internal Pull-Up if not usedNot Used
70VSSGNDSupply 0V
71VSSGNDSupply 0V
72PW7CPU_FAN_CTRLOutputActive-High - can be used for PWMCPU fan control
73PW6SEC_FAN_CTRLOutputActive-High - can be used for PWMBlade Server fan control
74P15Not UsedOutputActive-HighNot Used
75P14Not UsedOutputActive-HighNot Used
76P13Not UsedOutputActive-HighNot Used
77P12Not UsedOutputActive-LowNot Used
78P11Not UsedOutputActive-LowNot Used
79P10SER_ENABLE_LOutputActive-LowEnable console outputs
80CS4/HOST_CS4#InputActive-LowDecoded Xbus addr
81CS3/HOST_CS3#InputActive-LowDecoded Xbus addr
82HDB0HOST_D0I/OTri-StateXbus - South Bridge
83HDB1HOST_D1I/OTri-StateXbus - South Bridge
84HDB2HOST_D2I/OTri-StateXbus - South Bridge
85HDB3HOST_D3I/OTri-StateXbus - South Bridge
86HDB4HOST_D4I/OTri-StateXbus - South Bridge
87HDB5HOST_D5I/OTri-StateXbus - South Bridge
88HDB6HOST_D6I/OTri-StateXbus - South Bridge
89HDB7HOST_D7I/OTri-StateXbus - South Bridge
90HIRQ4HOST_IRQ4OutputActive-High, Totem-poleSouth Bridge
91HIRQ3HOST_IRQ3OutputActive-High, Totem-poleNot Used
92VSSGNDSupply 0V
93HA0HOST_A0InputAddress bit from XBusXbus - South Bridge
94CS2/HOST_CS2#InputActive-LowDecoded Xbus addr
95P82CPU_RST/OutputActive-Low, Open-DrainTo North Bridge
96P83SB_RST/OutputActive-Low, Open-DrainNot Used
97TXD1LOM_TXDOutputActive-LowTo SSP0 via Midplane
98RXD1LOM_RXDInputActive-LowTo SSP0 via Midplane
99SCL1HOST_SCLI/OActive-Low, Open-DrainTo DIMM SPD via Mux
100RESO/Not UsedOutput Not Used
Figure 4: BSC Signal List by Pin Number
4 I2C Map
The following drawing shows the I2C buses present in the Blade Server FRU and what is connected to them. The H8 I2C bus requires a pull-up to 5V to make the bus compatible with the 5V CMOS inputs on the H8. The AD1021 I2C inputs are 5V compliant. The bidirectional mux is configured to act as a level shifter between the 5V BSC segment of the bus and the 3V3 of the South Bridge. The hexadecimal values listed are seven-bit values. Because they do not include the read/write bit, they will require a left shift to convert to an eight-bit port value.
Figure 5: I2C Map
5 BSC Serial Ports
The two BSC serial ports connect to the midplane connector as out-of-band communications to the SSPs. This communication must be operational before the Blade Server FRU is powered up. Handshaking is listed below.
Figure 6: BSC Serial Ports
6 BSC Reset Control
The following diagram illustrates the reset circuit of the Blade Server FRU. This reset circuitry is designed to hold the Blade Server FRU in a reset state until it is commanded to start by the BSC power up sequence. The Blade Server Electrical requirements document covers the Blade Server power up sequence.
Figure 7: BSC Reset Control
7 Blade Server Power Circuitry
Blade Server power up is controlled by a Soft-Start that limits amperage influx. The BSC maintains the DCDC converters in a powered-off state. BSC is responsible for system checks and communications with the SSP. This holds the Blade Server FRU in a powered-off state until the Blade Server FRU is commanded to power up.
Figure 8: Generic DCDC Power Circuitry
8 References
Ref.Description
1Electrical Requirements of Blade Servers and FRUs -- Specification of electrical requirements
2System Overview of Blade Servers and FRUs -- Specification of system overview
3Mechanical Requirements of Blade Servers and FRUs -- Specification of mechanical requirements
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